1. Field of the Invention
This application is related to the field of circuit design, and more particularly to a software tool and method for accurately analyzing the timing requirements of a memory array.
2. Description of the Related Art
High-performance digital circuits have traditionally been characterized by the clock frequency at which they operate. Gauging the ability of a circuit to operate at the specified clock frequency requires an ability to measure the time it takes for signals to traverse paths through the circuit. While such timing measurements can theoretically be performed using a dynamic circuit simulation on a computer system, such an approach is often too slow or requires too many computing resources to be practical, especially if the circuit has a complex design.
Static timing analysis is a technique for computing the expected timing of a digital circuit without requiring a dynamic simulation. Static timing analysis generally involves traversing all the paths between endpoints in a circuit to determine the traversal time for each path by examining the timing characteristics of the hardware elements used in the path. The path that has the longest delay is referred to as the critical path. Static timing analysis plays a vital role in facilitating the fast and reasonably accurate measurement of circuit timing
Many digital circuits use memory arrays that are implemented as rows and columns of memory cells, where each cell stores a single bit. Memory arrays can have hundreds or thousands of memory cells. Because of their large size and the properties of the circuitry used to implement the cells, memory arrays can present problems for both dynamic simulation and static timing analysis. This can make it difficult to find the critical path through a memory array, which may in turn make it difficult to accurately analyze the timing requirements of a circuit that uses the memory array.